The present invention relates to a data extraction circuit used for reproduction of character data such as a closed caption and a text. More specifically, the present invention relates to a data extraction circuit used in a video signal reproduction circuit such as a television receiver and a video playback machine.
In a prior art data extraction circuit used for reproduction of character data, a CRI (clock run-in) signal is detected from a video signal on which character data such as a closed caption and a text is superimposed. Then, a clock signal for data reproduction is generated from the CRI signal, and the character data is reproduced in response to the clock signal.
FIG. 1 shows an overview of arrangement of a prior art data extraction circuit as described above. In this figure, an analog video signal, which is output from a video signal output terminal of a television receiver, is input to a video signal input terminal 101. A video signal on which a data line including character data such as a closed caption and a text is superimposed, or a normal video signal (on which no data line is superimposed) is input as the analog video signal. These analog video signals are supplied to an A/D converter (A/D) 102.
The A/D 102 converts the analog video signal, which is input to the video signal input terminal 101, into a digital video signal and then outputs it to both a CRI detection circuit 103 and a delay circuit 111.
The CRI detection circuit 103 detects whether the digital video signal (data line) output from the A/D 102 includes a CRI signal having eight cycles. If the CRI signal is included, it is supplied as a detection signal CRI to a slice level determination circuit 104 and a CRI level determination circuit 122 in a data reproduction clock generation circuit 120.
The slice level determination circuit 104 integrates the detection signal CRI output from the CRI detection circuit 103. The circuit 104 then supplies a DC level shift circuit 105 with a slice level determination signal having a level corresponding to an average of the integrated values.
The DC level shift circuit 105 shifts a level of the middle of an amplitude of a time-adjusted digital video signal (video 0), which is output from the delay circuit 111, based on the slice level determination signal output from the slice level determination circuit 104. The circuit 105 sends out the level-shifted digital video signal to a data reproduction circuit 106.
The delay circuit 111 delays the digital video signal output from the A/D 102 in accordance with time required until a clock signal is generated by the data reproduction clock generation circuit 120.
The data reproduction clock generation circuit 120 detects the detection signal CRI output from the CRI detection circuit 103 to generate a clock signal for reproduction of character data. The circuit 120 includes a clock generation circuit 121, the CRI level determination circuit 122, and a clock selection circuit 123.
The clock generation circuit 121 has two times as high as that of the detection signal CRI and generates two-phase clock signals CLK1 and CLK2 which are not synchronized with the detection signal CRI.
The CRI level determination circuit 122 compares the levels of detection signals CRI output from the CRI detection circuit 103 in respective timings of the two-phase clock signals CLK1 and CLK2 generated from the clock generation circuit 121. In response to the comparison result, the circuit 122 outputs determination signals CLKSEL of different logic levels to the clock selection circuit 123.
The clock selection circuit 123 is constituted of a combination of logic circuits such as an AND circuit and an OR gate. The circuit 123 obtains a difference between a logic level of the determination signal CLKSEL output from the CRI level determination circuit 122 and that of each of the two-phase clock signals CLK1 and CLK2 generated from the clock generation circuit 121. The circuit 123 then supplies a signal having a greater difference to the data reproduction circuit 106 as a data reproduction clock signal.
The data reproduction circuit 106 samples the digital video signal, which is level-shifted by the DC level shift circuit 105, in response to the data reproduction clock signal generated from the data reproduction clock generation circuit 120 and supplied from the clock selection circuit 123. Thus, the circuit 106 reproduces character data such as a closed caption and a text, which is superimposed on the digital video signal, and outputs it as reproduction data (1/0).
As described above, the prior art data extraction circuit is so constituted as to detect a CRI signal of eight cycles included in a data line and generate a clock signal for reproduction of character data.
If, however, the frequency (synchronization of horizontal/vertical sync signals) of an analog video signal varies, the data rate (cycle of CRI signal) of the data line does. Even though a clock signal for data reproduction can be generated, it is not synchronized with the CRI signal after the frequency varies). For this reason, in the prior art data extraction circuit for generating a clock signal for data reproduction by detecting a CRI signal contained in the data line, it is likely that the circuit cannot follow the frequency variations of an analog video signal or stably reproduce character data such as a closed caption and a text.
The object of the present invention is to provide a data extraction circuit capable of stably generating a clock signal for data extraction and stably reproducing character data, irrespective of variations in frequencies of video signals.
To attain the above object, there is provided a data extraction circuit comprising a slice level determination circuit configured to determine a slice level of a data line of character data superimposed on a digital video signal, a line extraction circuit configured to slice the digital video signal by the slice level and extract the data line of the character data from the digital video signal, a sync signal detection circuit configured to detect a sync signal for analyzing the character data, the sync signal being contained in the data line of the character data, a bit detection circuit configured to detect a start bit indicative of a start of the character data, the start bit being contained in the data line of the character data, a clock generation circuit configured to generate a data extracting clock, which is synchronized with a reference signal, based on detection results of the sync signal and the start bit, and a data reproduction section configured to reproduce the character data from the data line of the character data using the data extracting clock.
There is also provided a data extraction circuit comprising a first clock generation circuit for generating a system clock, which is synchronized with a reference signal, from a digital video signal on which standardized character data is superimposed as a data line, a slice level determination circuit for determining a slice level of the data line of the character data, a line extraction circuit for slicing the digital video signal by the slice level determined by the slice level determination circuit and extracting the data line of the character data from the digital video signal, a sync signal detection circuit for detecting whether a sync signal for analyzing the character data is present, from the data line of the character data extracted by the line extraction circuit, a bit detection circuit for detecting a start bit, which indicates a start of the character data, from the data line of the character data extracted by the line extraction circuit, a second clock generation circuit for generating a data extracting clock, which is synchronized with a reference signal, in response to the system clock generated by the first clock generation circuit based on detection results of the sync signal detection circuit and the bit detection circuit, and a data reproduction section for reproducing the character data from the data line of the character data extracted by the line extraction circuit, using the data extracting clock generated by the second clock generation circuit.
According to the data extraction circuit of the present invention, a data extracting clock signal can be generated based on a reference signal such as a horizontal sync signal and an fsc (subcarrier frequency) sync system clock signal. It is thus possible to resolve a drawback in which character data such as a closed caption and a text cannot be reproduced when an analog video signal varies in frequency.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.